(a) Field of the Invention
The present invention relates to a static random access memory (SRAM) device having a high soft error immunity and, more particularly, to an SRAM having excellent operation at Low supply voltage and a high soft error immunity through employing a new structure of a thin film transistor (TFT) load element;.
(b) Description of the Related Art
A conventional SRAM device having a TFT lead element is described, for example, in Publication Nos. JP-A-92-59783 and 92-162473. A memory cell structure of the SRAM device described in JP-A-92-162473 will be described below with reference to FIG. 1.
A memory cell of an SRAM generally has a flip-flop circuit formed by six transistors, namely, two drive transistors, two access transistors and two load TFTs. In FIG. 1, a gate electrode 24 of a load TFT is located under a channel region 25c of the lead TFT. Such an arrangement is called a "bottom gate type".
An access transistor is composed of heavily doped N-type source/drain regions 22a and 22b formed by diffusion in P-well region 31 located in an N-type semiconductor substrate 30 and a gate electrode 23a formed by a first polycrystalline silicon layer. A gate electrode 23c of each drive transistor is also formed by the first polycrystalline silicon layer. In FIG. 1, each of the gate electrode 24, source/drain electrodes 25a and 25b and a channel region 25c of the load TFT is located above the gate electrode 23c of the drive transistor with an intervention of an oxide layer. The gate electrode 24 of the load TFT is formed by a second polycrystalline silicon layer while the drain electrode 25a, the source electrode 25b and the channel region 25c are formed by a third polycrystalline silicon layer. The drain 22a of the access transistor is connected through a polycrystalline silicon pad 26 and a first metallic interconnection layer 27 to a bit line 28 formed by a second metallic interconnection layer.